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Hardware based algorithm for conflict diagnosis in SAT solver

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4 Author(s)
Safar, M. ; Ain Shams Univ., Cairo ; Shalan, M. ; El-Kharashi, M.W. ; Salem, A.

The Boolean satisfiability problem (SAT) is an NP-complete problem so software SAT's solving algorithm execution time influences the performance of SAT- based CAD tools. In this paper, we present a new approach for implementing conflict analysis based on a conflicting variables accumulator and priority encoder to determine backtrack level Using this approach, we implement an FPGA-based SAT solver performing depth- first search with conflict directed nonchronological backtracking. We compare our SAT solver with other SAT solvers through instances from DIMACS benchmarks suite.

Published in:

Computer Systems and Applications, 2008. AICCSA 2008. IEEE/ACS International Conference on

Date of Conference:

March 31 2008-April 4 2008