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This paper studies the effect of high performance pipelined GF(2256) bit-serial multiplier on elliptic curve point operations. A 3-stage pipelined version of the Massy-Omura GF(2m) normal basis multiplier for 160 lesm les 256 was studied in terms of area overhead and throughput improvement. Simple gate area and delay models were used to estimate the throughput of the pipelined and the non-pipelined multipliers. The proposed pipelined architecture has been shown to have a significant improvement in throughput allowing a single 3-stage pipelined multiplier to have higher throughput than an architecture employing three parallel non-pipelined multipliers. The AT2 performance metric has shown an even more significant improvement.