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To reduce the hardware complexity of finite-impulse response (FIR) digital filters, this paper proposes a new filter synthesis algorithm. Considering multiple adder graphs for a coefficient, the proposed algorithm selects an adder graph that can be maximally sharable with the remaining coefficients, whereas previous dependence-graph algorithms consider only one adder graph when implementing a coefficient. In addition, an addition reordering technique is proposed to derive multiple adder graphs from a seed adder graph generated by using previous dependence-graph algorithms. Experimental results show that the proposed algorithm reduces the hardware cost of FIR filters by 22% and 3.4%, on average, compared to the Hartley and -dimensional reduced adder graph hybrid algorithms, respectively.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:27 , Issue: 5 )
Date of Publication: May 2008