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A programmable clock generator HDL softcore

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5 Author(s)
Eisenreich, H. ; Univ. of Technol. Dresden, Dresden ; Mayr, C. ; Henker, S. ; Wickert, M.
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This paper presents a hardware implementation of a fully synthesizable, technology independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most 8 reference cycles. ASICs in CMOS AMS 0,35 um and UMC 0,13 um have been manufactured and tested. Measurements show competitive results to state-of-the- art mixed signal implementations.

Published in:

Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on

Date of Conference:

5-8 Aug. 2007