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Tri-Gate Bulk MOSFET Design for CMOS Scaling to the End of the Roadmap

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9 Author(s)
Xin Sun ; Univ. of California, Berkeley ; Qiang Lu ; Moroz, V. ; Takeuchi, H.
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A tri-gate bulk MOSFET design utilizing a low-aspect-ratio channel is proposed to provide an evolutionary pathway for CMOS scaling to the end of the roadmap. 3-D device simulations indicate that this design offers the advantages of a multi-gate FET (reduced variability in performance and improved scalability) together with the advantages of a conventional planar MOSFET (low substrate cost and capability for dynamic threshold-voltage control).

Published in:

Electron Device Letters, IEEE  (Volume:29 ,  Issue: 5 )

Date of Publication:

May 2008

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