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Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This is either unrealistic or impractical in many industrial situations. In this paper, we propose an architecture which implements classic low power encoding but uses industry standard DRAMs. Moreover, the low power encoding is combined with error-protection in order to extend the application to noisy channels or to the presence of soft and hard failures in the memory. Parallelism between the two encoding processes avoids any latency adder. Our experimental results, based on current consumption measurements of DDR2 DRAM components in mass production, show savings up to 31% on the I/O power and 6% on the total memory energy of a single channel memory system of 4 GB at practically no cost.
Date of Conference: 17-19 March 2008