Referenced Items are not available for this document.
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90 nm 26 kb SRAM module is reduced from 550 mV to 220 mV. A novel error-tolerant architecture further reduces the minimum static-error-free VDD to 155 mV. With a 100 mV noise margin, a 255 mV standby VDD effectively reduces the SRAM leakage power by 98% compared to the typical standby at 1 V VDD.
Published in:
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Date of Conference: 17-19 March 2008
- Page(s):
- 30 - 34
- Print ISBN:
- 978-0-7695-3117-5
- INSPEC Accession Number:
- 9896388
- Conference Location :
- San Jose, CA
- Digital Object Identifier :
- 10.1109/ISQED.2008.4479693
- Product Type:
- Conference Publications
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