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An eight megabit rad hard SRAM, implemented in 130 nm CMOS technology, uses stacked capacitors within the memory cell for robustness, supply power gating and internally developed array power supplies to achieve very low soft error rates and standby current consumption under 600 nA.
Published in:
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Date of Conference: 17-19 March 2008
- Page(s):
- 23 - 29
- Print ISBN:
- 978-0-7695-3117-5
- INSPEC Accession Number:
- 9896387
- Conference Location :
- San Jose, CA
- Digital Object Identifier :
- 10.1109/ISQED.2008.4479692
- Product Type:
- Conference Publications
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