By Topic

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Park, Ki-Tae ; Samsung Electron. Co., Ltd., Yongin ; Myounggon Kang ; Doogon Kim ; Soon-Wook Hwang
more authors

A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference which is well known as the most critical scaling barrier for NAND flash memories, a novel page architecture including temporary LSB storing program and parallel MSB program schemes is proposed. A BL voltage modulated ISPP scheme was used as parallel MSB programming in order to reduce cell-to-cell interference caused by the order in which the cells are programmed. By adopting the proposed page architecture, the number of neighbor cells that are programmed after programming a selected cell in BL direction as well as their amount of T/th shift during programming can be suppressed largely without increasing memory array size. Compared to conventional architecture it leads to a reduction of BL-BL cell-to-cell interference by almost 100%, and of WL-WL and diagonal cell-to-cell interferences by 50% at the 60 nm technology node. The proposed architecture enables also to improve average MLC program speed performance by 11% compared with conventional architecture, thanks to its fast LSB program performance.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 4 )