A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations

We have developed a circuit for determining an optimal supply voltage, V
_OPT
, for which energy consumption will be minimized in devices suffering from high-leakage. This V
_OPT
is determined on the basis of a trade-off between power consumption and operation time. Experimental results with a 90-nm CMOS device indicate that the proposed circuit successfully determines V
_OPT
with high accuracy. V
_OPT
operations with power gating at 40 MHz, and where V
_DD
= 0.67 V, results in an energy reduction of 52.8% over that achieved with DVFS alone at 5 MHz (1/20 of maximum operational frequency). Further, we propose a scheme for suppressing determination error, one that results in voltage error of less than 50 mV.