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A 12-bit nonlinear digital-to-analog converter (DAC) was fabricated in a 0.35-mum SOI CMOS process. The nonlinear DAC can implement a piecewise-linear approximation to a sine function and results in significant reduction of complexity and power dissipation when used in direct digital frequency synthesizers (DDFSs). The DDFS look-up table only needs to store offset and gain values for each segment. The look-up table size can be reduced from 11K bits to 544 bits for a 12-bit DDFS with 72 dB spurious-free dynamic range (SFDR). The nonlinear DAC consists of a 12-bit binary-weighted offset DAC and a multiplying DAC. The DACs use a current steering architecture for high-speed operation and the 5 most significant bits of the offset DAC are unary encoded to reduce glitches. The multiplying DAC consists of binary-weighted current sources switched by the partial products of the inputs. Test results show that the DAC has 12-bit accuracy after digital trimming, operates up to 600 MS/s and provides differential outputs of 0.5 V into 50 Omega loads. The SFDR is over 60 dBc below 20 MHz with a maximum of 72 dBc. Radiation tests show the nonlinear DAC can tolerate a total ionizing dose of 200 Krad Si.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:55 , Issue: 9 )
Date of Publication: Oct. 2008