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10-Gb/s Inductorless CDRs With Digital Frequency Calibration

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3 Author(s)
Che-Fu Liang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei ; Hong-Lin Chu ; Shen-Iuan Liu

Two 10-Gb/s inductorless clock and data recovery (CDR) circuits using different gated digital-controlled oscillators (GDCO) are presented. A digital frequency calibration is adopted to save the power consumption and chip area. They have been fabricated in 0.18-mum CMOS process. By using the complementary gating technique, the first CDR circuit occupies an active area of 0.16 mm2 and draws 36 mW from a 1.8 V supply. The measured rms jitter and peak-to-peak jitter is 8.5 ps and 42.7 ps , respectively. By using the quadrature gating technique, the second CDR circuit consumes an active area of 0.25 mm2 and its power consumption of 56 mW. The measured rms jitter and peak-to-peak jitter is 3.4 ps and 21.8 ps, respectively. The power of the second CDR circuit is higher than that of the first one but its jitter is reduced.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:55 ,  Issue: 9 )