Referenced Items are not available for this document.
This paper demonstrates a high performance silicon nanowire MOSFET built on silicon-on-insulator (SOI) platform. Stress-limiting oxidation technique was exploited for dual nanowire channel formation. To further improve the performance of the device, TaN metal gate is used instead of the conventional polysilicon gate. The thin silicon bridge between the two nanowires provides a small boost in the drive current, without degrading the short channel performance. The novel structures are able to achieve excellent electrical performances, high drive current of 927 muA/mum for p-channel and 554 muA/mum for n-channel, near ideal subthreshold slope (SS), and low drain-induced barrier lowering (DIBL).
Published in:
Nanotechnology, IEEE Transactions on
(Volume:7
,
Issue:
6
)
Date of Publication: Nov. 2008
- Page(s):
- 795 - 799
- ISSN :
- 1536-125X
- INSPEC Accession Number:
- 10370694
- Digital Object Identifier :
- 10.1109/TNANO.2008.917845
- Product Type:
- Journals & Magazines
- Date of Publication :
- 02 February 2008
- Date of Current Version :
- 30 December 2008
- Issue Date :
- Nov. 2008
- Sponsored by :
- IEEE Nanotechnology Council
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
