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A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations

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3 Author(s)
Ying Su ; Washington Univ., Seattle ; Holleman, J. ; Otis, B.P.

A 128-bit, 1.6 pJ/bit, 96% stable chip ID generation circuit utilizing process variations is designed in a 0.13 mum CMOS process. The circuit consumes 162 nW from a 1 V supply at low readout frequencies and 1.6 muW at 1 Mb/s. Cross-coupled logic gates were employed to simultaneously generate, amplify, and digitize the random circuit offset to create a stable unique digital chip ID code. A thorough statistical analysis is presented in order to explore the ID circuit reliability and stability. Two ID generators with different layout techniques were designed and fabricated to provide a performance comparison of power consumption, ID stability, and ID statistical robustness.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 1 )