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A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

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18 Author(s)
Ohbayashi, S. ; Renesas Technol. Corp., Hyogo ; Yabuuchi, M. ; Kono, K. ; Oda, Y.
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We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 x 36 mum2 using 65 nm technology.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 1 )

Date of Publication:

Jan. 2008

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