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An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit

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4 Author(s)
Shan Jiang ; Center for Integrated Circuits & Syst., Nanyang Technol. Univ., Singapore ; Do, A.V. ; Kiat Seng Yeo ; Wei Meng Lim

This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H) circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes the operational amplifier (opamp) gain, slew rate, bandwidth, and capacitor-matching requirements in pipelined ADCs. Due to the mixed-mode S/H technique, the single-stage opamps and small capacitor sizes can be used in this pipelined ADC, leading to a high speed and low-power consumption. Fabricated in a 0.18-mum CMOS process, the 8-bit pipelined ADC consumes 22 mW with 1.8-V supply voltage. When sampling at 200 MSample/s, the prototype ADC achieves 54-dB spurious free dynamic range and 45-dB signal-to-noise and distortion ratio. The measured integral nonlinearity and differential nonlinearity are 0.34 LSB and 0.3 LSB, respectively.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:55 ,  Issue: 6 )