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A Spur Elimination Technique for Phase Interpolation-Based Fractional- N PLLs

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2 Author(s)
Pamarti, S. ; Electr. Eng. Dept., California Univ., Los Angeles, CA ; Delshadpour, S.

A fractional spur elimination technique that enables wide-bandwidth phase interpolation-based fractional-N phase-locked loops (PLLs) is proposed. The technique uses specially filtered dither to eliminate the spurious tones otherwise caused by inevitable phase errors. The design of a wide-bandwidth fractional-N PLL based on the spur elimination technique and a theoretical proof of the proposed technique are presented.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:55 ,  Issue: 6 )