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15 nm Planar Bulk SONOS-type Memory with Double Junction Tunnel Layers using Sub-threshold Slope Control

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4 Author(s)
Ryuji Ohba ; Advanced LSI Technology Laboratory, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan. Phone: +81-45-776-5938, Facsimile: +81-45-776-4113, E-mail: ; Yuichiro Mitani ; Naoharu Sugiyama ; Shinobu Fujita

15 nm gate length bulk-planar SONOS-type memory device, which has Si nanocrystal layer lying between double tunnel oxides, retains 2.7 decades memory window for 10 years below 10 V write / erase (w/e) voltages. S-factor is controlled by source/drain (S/D) junction depth and channel concentration. It is experimentally shown that S to D direct tunneling determines a physical limit of S-factor control below 15 nm scale. Further device scaling and improvement by Si nanocrystal scaling are possible within the limit of S-factor control.

Published in:

2007 IEEE International Electron Devices Meeting

Date of Conference:

10-12 Dec. 2007