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As DRAM cell pitch size scales, the DRAM cells have required characteristics of high performance transistors. In this paper, we proposed and successfully demonstrated high performance silicon-on-ONO (SOONO) cell array transistors (SCATs) for 512Mb DRAM cell array application. They have advantages of SOI substrate and 3-D hi-gate as well as process simplicity. From those advantages, they have low Ioff due to good SCE immunity with DIBL of 40 mV/V and SS of 84 mV/dec, low GIDL current, low junction leakage current, and low junction capacitance as well as no body bias dependence. Thus, the SCATs may be a promising solution satisfying the requirements of DRAM cells with scaling.
Date of Conference: 10-12 Dec. 2007