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Memory Technologies for sub-40nm Node

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2 Author(s)
Kim, Kinam ; Samsung Electron. Co., Ltd., Yongin ; Gitae Jeong

Memory technologies for sub-40 nm will be reviewed, especially for DRAM and NAND Flash. First, technical challenges to be overcome in sub-40 nm node will be addressed, especially patterning and device's aspects. Then, possible solutions and directions will be discussed in detail. It is expected that memory technology scaling will be continued at least down to 30 nm node and beyond by developing novel structures and aggressively adopting new materials.

Published in:

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Date of Conference:

10-12 Dec. 2007