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With the market acceptance of small sized leaded packages migration to quad flat no lead version (QFN), an increasing number of large size semiconductor devices are being transferred into leadless platform to have foot print space advantage. Large QFN package behaves differently when subjected to stress tests compared to their predecessors. Package delamination and die crack are major challenges in achieving Pb Free reflow compatibility. Numerous combination of bill of materials, silicon wafer thickness, encapsulation thickness and leadframe design features contribution was studied. The initial screening experiment indicated that lead frame features, encapsulation thickness and die thickness are vital. Leadframe design with groove at the center of the die attach pad induces stress during temperature cycle that leads to silicon-leadframe interfacial separation. Groove at the package corners helps in reducing moisture ingression by enhancing mechanical locking. Encapsulation to die thickness ratio is recommended to be 4:1 to avoid package crack. Mold compound with lowest shrinkage factor and lowest moisture absorption helps in minimizing the delamination. Combination of above mentioned factors significantly improves the reliability of large leadless packages.