By Topic

Methods to Resolve Heel Stress for Ultra Thin QFN Small Package

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Siew Han Looe ; ON Semicond., Seremban ; Soon Wei Wang ; Aripin, A.

The current and future market demand for small, portable, compact and multi functional electronic products raises a great challenge to the semiconductor industries for small and thin package size, high quality, and high performance. The drive for package thickness thinning and package size reduction has created new challenges for current wire bonding technology which has led to small ball and low loop profile with largest possible wire size for the advantage of electrical performance. In the course of qualifying one of the ultra thin QFN (Quad Flat No-lead) small packages, gross heel stress was found at certain wire location in a high defect rate. First attempt in optimizing the wire bond power does not solve the heel stress problem. This indicates the complexity of the issue with existence of other significant influencing factors. DMAIC Methodology has been used to approach the problem in detail level. Several statistical analysis, design of experiment (DOE) and Finite Element Analysis (FEA) have been performed in order to narrow down to vital few. The FEA analysis in wire resonance has led the team to detail experiments in wire bonding sequence. Thorough analysis (through DOEs and statistical analysis) has been performed to identify the most optimized looping profile in distributing the ultrasonic power effectively. Package layout is fully explored as well to identify opportunities in improving the robustness of wire bonding. This paper explains in detail the hypothesis, statistical analysis, DOEs and FEA that have been performed to identify the root causes of this particular heel stress issue using DMAIC methodology. It is proven that the convergence of data driven and experience driven analysis through DMAIC methodology is the key to the success of this project. The convincing result shows that lead frame design, wire bonding direction, sequence, and loop profile are significant factors. This paper also illustrates all the solutions employed not only to eliminat- e the heel stress problem, but to enhance robustness in wire bonding as well.

Published in:

Electronic Manufacturing Technology Symposium, 2007. IEMT '07. 32nd IEEE/CPMT International

Date of Conference:

3-5 Oct. 2007