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A novel dynamic scheduling algorithm of data hazard for embedded processor

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3 Author(s)
Jiajing Lu ; Fudan Univ., Shanghai ; Xiaofang Zhou ; Junyu Wang

To solve the data hazard of embedded processor, this paper designs a dynamic scheduling algorithm to improve the pipeline efficiency, which only increases one single-instruction buffer and some combination logic. In FFT and FIR experiment, the algorithm leads to the decrease of the pipeline conflict to 100% and 75% respectively. There is 8.2% additional area of the whole processor.

Published in:

ASIC, 2007. ASICON '07. 7th International Conference on

Date of Conference:

22-25 Oct. 2007