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This paper describes a 1.8-V, 8-bit, 125 Msample/s analog-to-digital converter (ADC) with a power-efficient architecture designed in a 0.18-mum CMOS technology. Through sharing an amplifier between two successive pipeline stages, the converter is realized with just three amplifiers and a separate sample-and-hold block. It employs a wide-bandwidth low-power wide-swing gain-boosting folded-cascode amplifiers, an improved bootstrap switch technique and appropriate scaling down skill. The simulation result shows the ADC achieves 57.7 -dB spurious free dynamic range (SFDR), 48- dB signal-to-noise ratio (SNR), 7.6 effective number of bits (ENOB) for 62- MHz input and consumes 36 - mw from 1.8-V supply, which also includes five buffer amplifiers.