Notice of Violation of IEEE Publication Principles: A Single-Conversion SiGe BiCMOS Satellite TV LNB Front-End Using an Image Reject Mixer and a Calibrated Full-Rate VCO

Notice of Violation of IEEE Publication Principles

"A Single-Conversion SiGe BiCMOS Satellite TV LNB Front-End Using an Image Reject Mixer and a Calibrated Full-Rate VCO"
by Maxim, A.; Gheorghe, M.; Smith, D.;
in the Proceedings of the IEEE Custom Integrated Circuits Conference, 2007. CICC '07
16-19 Sept. 2007 Page(s):97 - 100

After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.

Specifically, Adrian Maxim admitted the information in the paper was falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.
A fully-integrated satellite TV down-converter was realized in a 0.18 mum SiGe BiCMOS process that provides both 70 GHz f
_T
NPNs used for the main signal path and 0.18 mum CMOS FETs used for the frequency synthesizer reference clock path and LC-VCO frequency calibration circuitry. A low phase-noise, low tuning gain 10 GHz LC-VCO that covers both low and high Ku-bands was realized by combining a 30% discrete steps frequency calibration with a 2% continuous frequency tuning. Offset-biased accumulation MOS varactors provide a virtually constant tuning gain by summing shifted C(V) curves that are uniformly distributed over the entire control voltage range. The on-chip synthesizer loop filter eliminates the sensitivity to off-chip noise and spur coupling. Mixer's noise was reduced by using an image-reject architecture that attenuates the thermal noise contribution from the image frequency. The LNB performance includes: <6 dB noise figure, 18 dBm output IP3, -106 dBc/Hz phase noise at lOOKHz offset, <0.4deglms total integrated phase noise, 1.7x1.5 mm die area and 125 mA bias current from a 3.3 V supply.