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Clock distribution is a major issue when implementing system-on-a-chip in deep sub-micron technologies. This work presents a new mesochronous physical link architecture, named SKIL, which enables full bandwidth communication between macrocells clocked by signals with the same frequency and an arbitrary amount of skew. SKIL is implemented using standard-cells design flows. It introduces two clock cycles of latency and negligible area and leakage power overheads. Implementation results are presented on a 65 nm CMOS technology.