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Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip

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3 Author(s)
Eric Cheung ; Department of Computer Science and Engineering, University of California Riverside, Riverside, 92521, USA ; Harry Hsieh ; Felice Balarin

Multiprocessor System-on-Chip (MPSoC) has emerged as the most promising architecture for future embedded system designs, and Kahn Process Networks (KPN) have been shown to be an excellent solution to model applications for MPSoC because it allows maximum freedom in implementation. However, the effects of buffer sizing for KPN applications on MPSoC are not well investigated. Sizes for the bounded FIFOs affect the parallelism in the implementations and the performance of the systems. To the best of our knowledge, buffer sizing for performance optimization in MPSOC has not been addressed before. We propose an off-line automatic buffer sizing algorithm based on the rate constraints and the dependency information gathered from the profiled results. The algorithm can be applied to rate-constraint application such as MPEG-2 decoder to determine the minimum buffer sizes that satisfies the constraints. Our study shows that our algorithm can automatically size the buffers such that the total buffer usage is reduced by orders of magnitude for a given rate constraint.

Published in:

High Level Design Validation and Test Workshop, 2007. HLVDT 2007. IEEE International

Date of Conference:

7-9 Nov. 2007