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Efficient Hardware/Software Implementation of an Adaptive Neuro-Fuzzy System

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4 Author(s)
del Campo, I. ; Dept. of Electr. & Electron., Univ. of the Basque Country, Leioa ; Echanobe, J. ; Bosque, G. ; Tarela, J.M.

This paper describes the development of efficient hardware/software (HW/SW) neuro-fuzzy systems. The model used in this work consists of an adaptive neuro-fuzzy inference system modified for efficient HW/SW implementation. The design of two different on-chip approaches are presented: a high-performance parallel architecture for offline training and a pipelined architecture suitable for online parameter adaptation. Details of important aspects concerning the design of HW/SW solutions are given. The proposed architectures have been implemented using a system-on-a-programmable-chip. The device contains an embedded-processor core and a large field programmable gate array (FPGA). The processor provides flexibility and high precision to implement the learning algorithms, while the FPGA allows the development of high-speed inference architectures for real-time embedded applications.

Published in:

Fuzzy Systems, IEEE Transactions on  (Volume:16 ,  Issue: 3 )

Date of Publication:

June 2008

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