Referenced Items are not available for this document.
We have extensively studied stress enhancing techniques to increase channel mobility starting at the 130 nm technology node and continued this towards the 45 nm node. Stressed overlayers and spacer materials, strained SOI substrates, embedded SiGe and SiC layers and their proximity effects, the impact of different silicides, stress memorization and compatibility with laser and flash anneals have been investigated. The integration of abovementioned techniques into a CMOS flow resulted in an outstanding pMOS and nMOS performance improvement, no reliability issues and no impact on short channel behavior.
Published in:
Advanced Thermal Processing of Semiconductors, 2007. RTP 2007. 15th International Conference on
Date of Conference: 2-5 Oct. 2007
- Page(s):
- 19 - 29
- E-ISBN :
- 978-1-4244-1228-0
- Print ISBN:
- 978-1-4244-1227-3
- INSPEC Accession Number:
- 10018548
- Conference Location :
- Catania, Sicily
- Digital Object Identifier :
- 10.1109/RTP.2007.4383814
- Product Type:
- Conference Publications
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