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High Speed Direct Digital Frequency Synthesizer(DDFS) Architecture With Reduced ROM Structure

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4 Author(s)

A low-power, high speed direct digital frequency synthesizer (DDFS) is presented. Some approximations are used to avoid using a large ROM look-up table to store the trigonometric values in a conventional DDFS. Significant saving in power consumption, due to the compressed ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a DDFS has been implemented using useful trigonometric equations. The spurious-free dynamic range is about 60 dB at low synthesized frequencies.

Published in:

Engineering Sciences and Technology, 2005. SCONEST 2005. Student Conference on

Date of Conference:

27-27 Aug. 2005