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On-Chip Interconnection Architecture of the Tile Processor

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10 Author(s)
Wentzlaff, D. ; Massachusetts Inst. of Technol, Cambridge ; Griffin, P. ; Hoffmann, H. ; Liewei Bao
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IMesh, the tile processor architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. taking advantage of the five networks, the C-based ILIB interconnection library efficiently maps program communication across the on-chip interconnect. the tile processor's first implementation, the tile64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 Ghz.

Published in:

Micro, IEEE  (Volume:27 ,  Issue: 5 )

Date of Publication:

Sept.-Oct. 2007

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