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The occurence of periodic Coulomb blockade in transistors at low temperature allows to extract the capacitances between the channel and the gate, source, and drain. This extremely sensitive method is well adapted to nanoscale devices, where these capacitances are well below the fF range and in parallel with low resistances. We applied this method to 3-D stacked MOSFETs featuring a double-gate top channel and a single-gate bottom channel. The measured gate capacitances are in excellent agreement with estimations based on the geometry, and are independent on the gate voltage. The source and drain capacitances can also be measured separately for each parallel conduction channel, even when their values are markedly different. We illustrate this case with a device with one dominating double-gate channel and a buried, single-gate channel which is not detectable at 300 K and contributes for less than 5% to the total conductance at 4.2 K.