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Distributed Arithmetic for FIR Filter Design on FPGA

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3 Author(s)
Wang Sen ; Univ. of Electron. Sci. & Technol. of China Chengdu, Chengdu ; Tang Bin ; Zhu Jun

This paper presents a distributed arithmetic (DA) for highly efficient multiplier-less FIR filter designed on FPGA. First, the theory of the distributed arithmetic is described. Furthermore, a modification of the DA based on the look up table (LUT) and filter structure to implement the high-order filter hardware-efficient on FPGA is introduced. The proposed filter has been designed and synthesized with ISE 7.1, and implemented with a 4VLX40FF668 FPGA device. Our results show that the proposed DA architecture can implement FIR filters with the smaller resource usage and similar speed in comparison to the previous DA architecture.

Published in:

Communications, Circuits and Systems, 2007. ICCCAS 2007. International Conference on

Date of Conference:

11-13 July 2007