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High-Voltage-Tolerant Analog Circuits Design in Deep-Submicrometer CMOS Technologies

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5 Author(s)

Electrical stress-relieved analog circuit design techniques using only baseline devices are presented, 1-to-2 logic level shifter, optional diode insertion, and adaptive biasing scheme are introduced to meet a reliability guideline that ensures sufficient lifetime. The proposed idea was successfully demonstrated with 12-bit I/Q digital-to-analog converter (DAC) and an operational amplifier having a Classs-AB output stage in 65-nm n-well CMOS technology and a high temperature operating life (HTOL) test was performed to evaluate the reliability of the design.

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IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:54 ,  Issue: 10 )