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Development of Integrated Broad-Band CMOS Low-Noise Amplifiers

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2 Author(s)
Yi-Jan Emery Chen ; Nat. Taiwan Univ., Taipei ; Yao-I. Huang

This paper presents a systematic design methodology for broad-band CMOS low-noise amplifiers (LNAs). The feedback technique is proposed to attain a better design tradeoff between gain and noise. The network synthesis is adopted for the implementation of broad-band matching networks. The sloped interstage matching is used for gain compensation. A fully integrated ultra-wide-band 0.18-mum CMOS LNA is developed following the design methodology. The measured noise figure is lower than 3.8 dB from 3 to 7.5 GHz, resulting in the excellent average noise figure of 3.48 dB. Operated on a 1.8-V supply, the LNA delivers 19.1-dB power gain and dissipates 32 mW of power. The gain-bandwidth product of the UWB LNA reaches 358 GHz, the record number for the 0.18-m CMOS broad-band amplifiers. The total chip size of the CMOS UWB LNA is 1.37 times 1.19 mm2.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:54 ,  Issue: 10 )