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An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise

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3 Author(s)
Nakamura, Y. ; Tokyo Univ., Tokyo ; Takamiya, M. ; Sakurai, T.

An on-chip noise canceller with high voltage supply lines for the nanosecond-range power supply noise is proposed. The canceller fabricated with 90-nm CMOS achieves 68% noise reduction with 2.0% power increase. Under the same noise reduction conditions, the area penalty for the canceller is 1/77 and 1/45 of those for the additional on-chip decoupling capacitors and the power supply lines respectively.

Published in:

VLSI Circuits, 2007 IEEE Symposium on

Date of Conference:

14-16 June 2007

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