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A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography

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4 Author(s)
Ghosh, S. ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India ; Alam, Monjur ; Gupta, I.S. ; Chowdhury, D.R.

This paper presents the architecture and FPGA implementation of a robust GF(p) parallel arithmetic unit. The most efficient modular multiplication, inversion and division units greatly reduce the clock cycles requirement for point operations applicable to elliptic curve cryptography. The parallel arithmetic unit helps to achieve a high speed up in cryptographic applications. The architecture can resist the cryptographic timing attack. Integrated input and output interface units provide lower bandwidth requirement to plug in the architecture with automated cryptographic systems. The design exhibits its elegance among competitive architecture with respect to throughput and robustness.

Published in:

Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on

Date of Conference:

29-31 Aug. 2007