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Improving Yields of High Performance 65 nm Chips with Sputtering Top Surface of Dual Stress Liner

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9 Author(s)
Huilong Zhu ; IBM System & Technology Group at IBM Semiconductor Research and Development Center (SRDC), Hopewell Junction, NY 12533 ; Daewon Yang ; Mahender Kumar ; John Colt
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This paper presents a simple, effective, and economical method to improve the yield of high performance 65 nm SOI CMOS technology using dual stress nitride liner (DSL) for performance enhancement. Sputtering is used to reduce the complexity caused by DSL boundaries to smooth/trim the top surface of the DSL, which results into a significant yield increase. The perfect yield of 36 Mb 0.65 mum2 SRAM is increased by 25%. The yield for dual-core microprocessors is increased by 33% and for single-core microprocessors by 75%. Yield improvement is explained and sputtering effects on DSL stress and device performance are discussed. This method is in qualification process for product manufacturing.

Published in:

2007 IEEE Symposium on VLSI Technology

Date of Conference:

12-14 June 2007