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The algorithm of embedded block coding with optimization truncation (EBCOT) is one of the key techniques in JPEG2000 standard. The high-speed/performance hardware designs for EBCOT are critical to various high-resolution applications, such as digital cameras, digital video recorders, and HDTV, etc. This paper presents a detailed performance analysis for EBCOT Tier-1 and its bit plane parallel architecture design. By analyzing the bit plane parallel context modeling, we conclude that the difference between the output rate of context modeling module and that of arithmetic coding module degrades the performance of whole EBCOT parallel encoding. We propose two improved methods, referred to as data-pairs ordering (DPO) and flexible MQ (FMQ) coder. It solves the configuration problem between the parallel context modeling module and the sequent arithmetic coding module, takes full advantage of the bit plane parallel encoding technique, and improves the coding speed and efficiency of the EBCOT encoder significantly. The design of parallel EBCOT encoder is tested on the field-programmable gate array (FPGA) platform of Altera Company. The simulation results show that it can on average encode 54 million samples at 55-MHz working frequency. It is equivalent to encoding a 90006000 image per second or encoding 720 p (1280times720, 4:2:2) HDTV picture sequence nearly 30 frames per second. Compared with the conventional bit plane parallel architecture design, the proposed one can reduce execution time by 24%.
Circuits and Systems for Video Technology, IEEE Transactions on (Volume:17 , Issue: 10 )
Date of Publication: Oct. 2007