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Two new high-performance bidirectional mixed radix-2n serial-serial multipliers are presented. The new designs have improved the area-time performance by ~31% when compared with existing radix-2n serial-serial multipliers. The second design is the first twin-pipe bidirectional radix-2n serial-serial multiplier reported in the literature. The twin-pipe multiplier can be used to perform two successive K-digit multiplications in 2K + 6 cycles without truncating the results. As a consequence, new data can be fed into the multiplier every K+3 cycles. Both proposed designs possess the scalability feature that is missing in existing radix-2n serial-serial multipliers because of the storage elements, which depend on the number of digits needed at the front-end to ensure correct functionality. As a final remark, another significant aspect of the proposed mixed radix-2n serial-serial architecture and its twin-pipe version is that they can be pipelined to the bit-level and give the designer the flexibility to obtain the best trade-off between throughput rate and hardware cost by varying the digit size and the number of pipelining levels.