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Built-in self-test (BIST) is a key design-for-testability technique for digital systems in nanometre technologies. BIST design is usually quite intrusive. In fact, BIST-per-scan or BIST-per-clock schemes require the replacement of all circuit registers by modified flip-flops or registers with extra functionality, which may lead to unacceptable area overhead and, especially, performance degradation. However, for some applications, system performance cannot be compromised by BIST insertion. Moreover, many applications have multiple clock domains and need to be self-tested at speed, during product lifetime. The functional-oriented mask-based BIST is proposed as a minimum impact BIST design methodology. The proposed approach uses testability metrics and circuit functionality to iteratively obtain a BIST solution with the required fault coverage (FC). It can be implemented in multiple clock domain designs and lead to short BIST sessions and a limited impact on system performance. A real world case study, for which system performance is critical, is used to demonstrate that high FC values in a sequential circuit can be achieved, operating at-speed with multiple clock signals, with minimum performance degradation and with lower hardware overhead than the one obtained with a BIST-per-scan solution. The case study is a two-clock domain Sync core for the synchronisation and link board of electromagnetic calorimeter and hadron calorimeter detectors of the CERN compact Muon solenoid experiment.