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A BIST architecture is presented to perform charge-based testing (BIST-CBT) on embedded memories where direct access to I/Os is limited. The proposed architecture includes a charge monitor, a functional test algorithm generator (that applies a standard March B algorithm) and output processing circuitry. The method is based on a charge correlation technique validated experimentally on previous works for submicron SRAMs. The testing methodology implementation has two phases: a short pre-characterisation phase performed during manufacturing test to ensure process-variation immunity, and the actual BIST-CBT. Data from the first phase are processed and loaded in the BIST circuitry registers. The proposed embedded BIST circuitry provides a digital output pass/fail flag that signals the result of the functional and BIST charge analysis (both based on the same March algorithms). To demonstrate the viability of the proposed architecture, a prototype is designed that has been implemented in two parts: the charge monitor is the core of the BIST circuitry, and has been developed in 120 nm CMOS technology, whereas the digital processing circuitry has been implemented on a FPGA device.