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BiMOS transistors: merged bipolar/sidewall MOS transistors

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3 Author(s)
O, K.K. ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; Reif, Rafael ; Hae-Seung Lee

The concept and feasibility of merged bipolar/sidewall MOS transistors (BiMOS transistors) are demonstrated by fabricating and characterizing the structures. The NMOS-input Darlington pair was merged into an NMOS-input BiMOS Darlington transistor which occupies 1.2 times the area of a single n-p-n bipolar transistor. It should be possible to form other BiCMOS subcircuit elements such as the PMOS-input BiMOS Darlington transistor and BiCMOS static memory cell. An initial analysis of the doping requirements for the base of the n-p-n bipolar transistor and the channel of the sidewall MOS transistors suggests that the requirements are compatible.<>

Published in:

Electron Device Letters, IEEE  (Volume:10 ,  Issue: 11 )

Date of Publication:

Nov. 1989

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