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Sub-300-ps CBL circuits

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9 Author(s)
Widemann, S.K. ; IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA ; Chen, T.-C. ; Ching-Te Chuang ; Heuber, K.
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Advanced charge-buffered-logic (CBL) circuits featuring double-poly self-alignment, a 'free' epi-base lateral p-n-p (cutoff frequency=300 MHz only), and deep trench isolation are discussed. Using 1.2- mu m design rules and a modified push-pull output stage, a gate delay (fan-in=3) of 278 ps was obtained at a DC current of 30 mu A/gate. The low power-delay product underlies the speed and power potential of CBL as an attractive practical approach to bipolar complementary transistor logic.<>

Published in:

Electron Device Letters, IEEE  (Volume:10 ,  Issue: 11 )

Date of Publication:

Nov. 1989

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