Limitation of spacer thickness in titanium salicide ULSI CMOS technology

The isolation integrity of various gate-spacer thicknesses in 15-20- mu m-wide MOS devices with and without titanium salicide is discussed. The gate-spacer thickness varies from 25 to 100 nm. Experimental results show that for Ti salicided devices with only a 25-nm-thick gate spacer, a broad spectrum of gate-drain (source) breakdown voltages, at a leakage current level of 2 mu A, is measured in the range of 1.5 to 10 V. Using a specific gate-spacer tester with a total gate-spacer perimeter near 10 cm in length, the statistical data taken over 100 tested chips show that as the thickness of the gate spacer is reduced to less than 50 nm, the gate leakage increases to 10/sup -9/ A under a gate bias equal to 5 V. The leakage of the thin gate spacer is attributed to the formation of Ti-rich oxide during the Ti self-aligned silicide process, which degrades the isolation integrity and generates a leakage path. The implications of this leakage mechanism for ULSI technologies are discussed.<>