Implementation of Fast Fourier and Inverse Fast Fourier Transforms in FPGA

This article explains implementing of fast Fourier (FFT) and inverse fast Fourier transform (IFFT) algorithms in FPGA. The reason of designing the study on FPGA base is that FPGAs are able to rearrange of logical blocks and moreover, mathematical algorithms can confirm faster by means of parallel data processing. For operating these algorithms, it was used the family of Xilinx Virtex2P xc2vp30fg676-7 FPGA device as a hardware in this study. In programming the hardware and writing codes, VHDL was used. The results show that FFT and IFFT algorithms result in 0.6 mus and 0.72 mus cycle time respectively.