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A 4-GS/s 4-bit Flash ADC in 0.18- μm CMOS

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3 Author(s)
Sunghyun Park ; Qualcomm Inc., Campbell ; Yorgos Palaskas ; Michael P. Flynn

A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10-11 at 4 GS/s.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:42 ,  Issue: 9 )