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Halo and LDD Engineering for Multiple VTH High Performance Analog CMOS Devices

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1 Author(s)
Jyh-Chyurn Guo ; Nat. Chiao-Tung Univ., Hsinchu

High performance analog (HPA) CMOS devices with multiple threshold voltages have been successfully fabricated in a 0.13-mum logic-based mixed-signal CMOS process on a single chip. The HPA devices demonstrate superior drivability, dc gain, matching, and reliability using an optimized halo and lightly doped drain (LLD) engineering approach combined with a unique dual gate oxide module for aggressive gate oxide thickness scaling.

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:20 ,  Issue: 3 )

Date of Publication:

Aug. 2007

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