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Watermark-Induced High-Density Via Failures in Submicron CMOS Fabrication (May 2006)

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7 Author(s)
Alex Chew ; Silicon Manuf. Co., Singapore ; Hing Ho Au ; S. H. Han ; T. L. Neo
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High via resistance was detected in the high-density via structure in our 0.15-mum back-end-of-line (BEOL) yield monitoring test vehicle. A localized insulating layer was found on top of the plug in test vehicle causing high via resistance. The failure was attributed to watermark-induced contaminants on top of the W plug. It was shown that the failure could be avoided by eliminating watermark formation on the wafer in the post-chemical-mechanical polishing scrub process.

Published in:

IEEE Transactions on Semiconductor Manufacturing  (Volume:20 ,  Issue: 3 )