Numerical Simulation of Low-Frequency Noise in Polysilicon Thin-Film Transistors

Numerical simulations of low-frequency noise are carried out in two technologies of N-channel polysilicon thin-film transistors (TFTs) biased from weak to strong inversion and operating in the linear mode. Noise is simulated by generation/recombination processes. The contribution of grain boundaries on the noise level is higher in the strong inversion region. The microscopic noise parameter that is deduced from numerical simulations is lower than the macroscopic one defined according to the Hooge empirical relationship and deduced from noise measurements. The higher macroscopic value is attributed to the drain-current crowding induced by nonconducting spots in the devices due to structural defects. The ratio of these two noise parameters can be considered as an indicator to qualify TFT technology.